An Efficient Viterbi Decoder For Low Complexity

Volume 5, Issue 3, March – 2020 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
An Efficient Viterbi Decoder for Low Complexity,

High Performance Digital Systems
Almukhtar Ahmed 1
Faculty of Engineering, Sabratha University, SABRATHA, LIBYA
Abstract:- The level of circuit performance which can The Add Compare Select Unit (ACSU) is described as
be reached with in certain design time mainly depends all Branch Metrics (BM) to the following Path Metrics
on the efficiency of the design methodologies as well as (PM). The new PM will be thought about and the chose PM
on the design style. In digital design researchers will be put away in the Path Metric Memory (PMM).
interesting in decrease the consumed power, area as Simultaneously, the ACSU stores the related survivor way
result the speed of the system increases. By using choices in the Survivor Memory Unit (SMU).The PM of
reversible logic which has advantages over traditional the survivor way of every state is refreshed and put away
one such as decrease gate counts and garbage output in inside the PMM. The rest of the Memory Unit utilizes the
addition to constant inputs. In this paper design of Trace-Back technique to recognize the survivor way and
Viterbi decoder based reversible gates is presented and yield information. The decoded bits which are included in
verified using Xilinx. this unit will be eliminated from the beginning through
minimal way metric.
Keywords:- Reversible Gates, Viterbi Decoder, Simulations
and Results . Initially start with second state, in reverse following is
5 went after by the 6 survivor way, initially first added to
I. INTRODUCTION the 8 and a 9 one way is distinguished. While tracking2
back 3through the trellis, the decoded 5output succession
The Viterbi translating calculation was presented by corresponding7 to the traced8 branches9 is generated0 in
Andrew J Viterbi, which is a decoding process for the switch request.
convolutional codes in memory-less clamor. This
calculation is actualized in the structuring of II. REVERSIBLE LOGIC
correspondence frameworks. The Viterbi Algorithm is the
most asset expending and it finds the probably quiet case Reversible registering is the utilization of standards of
progress grouping in a state graph, given an arrangement of reusing to figuring. A reversible rationale door is mapped
images which are hindered by clamor [2]. For the most with coordinated rationale gadget having a n-input, n-yield
part, a Viterbi decoder consists of three main calculation entryway. As it discovers the yields from sources of info
units: fig 1 despite the fact that the information sources can be only
recouped from the yields. In the vital conditions to have the
quantity of sources of info equivalent to the quantity of
yields extra data sources or yields is included. A significant
requirement presents on the structure of a reversible
rationale circuit utilizing reversible rationale door is that
the fan-out isn't permitted. The quantum cost of reversible
rationale circuits must be least. With the base number of
reversible doors, the structure of reversible circuit is
cultivated.
The real limitation to accomplish enhancement of the

circuit is to deliver the trash yields and the consistent
Fig 1:- Main parts of Viterbi decoder contributions with the base number. The reversible
rationale entryways are the circuits which has number of
Main part is known as branch metric unit (BMU), sources of info is equivalent to number of yields.
which contrasts the got information images and the perfect
yields of the encoder lastly the branch metric will be The significant improvement parameter for each
determined. The Euclidean separation or Hamming reversible rationale entryway is the quantum price [4]. The
separation which is applied for the computation of BMU. necessary elements for Viterbi decoder are listed below:
The BMU creates branch measurements for the
accompanying module regarding the images obtained by
the channel.
IJISRT20MAR486 www.ijisrt.com 1209

ISSN No:-2456-2165
 Feynman Gate III. SIMULATION AND RESULTS
The Feynman door is 2x2 reversible entryway which
include the information sources (A, B) and produce (P =A, The proposed Viterbi decoder is simulated by Verilog
Q = A B). This door is likewise alluded same Controlled coding and recreated. And simulation results are shown in
NOT. The quantum price is 1. This is chiefly utilized for figs ( 5-17) The most important parameters for evaluate
the fan-out capacity. The used power and deferral are VLSI configuration are area, power and speed. Table 1
17mW and 7.761ns [3]. summarize The execution power report and
Table2summarize area and timing report.
Fig 2:- Feynman Gate
 Peres Gate
The Peres door is 3x3 reversible entryway, in which
the A, B,C are the sources and P, Q and R are represented Fig 5:- RTL design with reversible logics
outputs . The outputs are mapped as P =A, Q = A B and R=
A.B C. The quantum price is 4,and the used power and time
are 24mW ,7.824nsrespectivily.
Fig 3:- Peres Gate
 HN Gate
The HNG is a 4x4 reversible gate with four inputs A,
B, C, D and four outputs P, Q, R, S, where P=A, Q= B, R=
A B C and S= (A B) C AB D. The quantum price is 6 and Fig 6:- Compute Metric Unit RTL design
the consumed power with delay are 24mW and 7.823ns.
Fig 4:- HN Gate

Fig 7:- Compute block of RTL design

ISSN No:-2456-2165
Fig 12:- Reduced Unit design ( RTL )
.
Fig 8:- Metric Unit design (RTL)
Fig 13:- Reduced Unit design with two inputs
Fig 9:- Design of Metric unit with D flip flop
Fig 14:- path memory unit design(RTL)
Fig 10:- ACS-Enable Unit design(RTL)

.
Fig 15:- multiplexer units 4x1)
Fig 11:- Compare Select Unit design(RTL) Fig 16:- Buffer unit with D-flip flop

ISSN No:-2456-2165
IV. RESULTS AND DISCUSSION
Table 1:- Power Performance Summary
Table 2:- Summary Performance of Area and Timing
V. CONCLUSION
In this paper vertibi decoder is designed using

reversible logic gates which have advantages over classic
gates such as reduction in consumed power and reducing
area. The designed decoder is verified by Xilinx and the
results showed that it has less power consumption and less
area so it may be used in high performance digital systems.
REFERENCES
[1]. D. Chakraborty, P. Raha, A. Bhattacharya, "Speed

Fig 17:- Output waveforms Optimization of a FPGA Based Modified Viterbi
Decoder", International Conference on Computer
Communication and Informatics (ICCCI), January
2013.
[2]. Abdulfattah M. Obeid, Alberto Garcia, "A Multipath
High Speed Viterbi Decoder", IEEE 2003: pp.1160-
1163.

ISSN No:-2456-2165
[3]. T. Toffoli, "Reversible Computing," Technical
Report MIT/LCS/TM- 151, 1980.
[4]. R. Feynman, "Simulating Physics with Computers,"
International Journal of Theoretical Physics, 1982.
[5]. A. Peres, Reversible Logic and Quantum
6,1985.pp3266-3276.Computers,” Physical Review,
vol. 32, iss.
[6]. Papiya Biswas, Namit Gupta, Nilesh Patidar,”Basic
Reversible Logic Gates and its Qca Implementation”
Vol. 4, Issue 6(Version 5),June2014.
[7]. H.R.Bhagyalakshmi,M.K.Venkatesha,’optimized
Reversible BCD adder using new Reversible Logic
Gates’ Journal ofComputing, Vol 2, Issue 2, and
February2010.
[8]. Abu Sadat Md. Sayem, Masashi Ueda.’ Optimization
of reversible sequential circuits’ Journal of
Computing, Volume 2, Issue6, June 2010, ISSN 2151-
9617.
[9]. Md. Belayet Ali , Md. Mosharof Hossin and Md.
Eneyat Ullah, ‘Design of Reversible Sequential
Circuit Using ReversibleLogic Synthesis’
International Journal of VLSI design &
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December2011.
[10]. Rakshith Saligram, Rakshith T.R, ‘Novel Code
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[11]. K. Biswas, M. M. Hasan, A. R. Chowdhury, and H.
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An Efficient Viterbi Decoder For Low Complexity

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Volume 5, Issue 3, March – 2020 International Journal of Innovative Science and Research Technology

An Efficient Viterbi Decoder for Low Complexity,

The real limitation to accomplish enhancement of the

IJISRT20MAR486 www.ijisrt.com 1209

Fig 2:- Feynman Gate

Fig 3:- Peres Gate

Fig 4:- HN Gate

IJISRT20MAR486 www.ijisrt.com 1210

Fig 12:- Reduced Unit design ( RTL )

Fig 13:- Reduced Unit design with two inputs

Fig 9:- Design of Metric unit with D flip flop

Fig 14:- path memory unit design(RTL)

Fig 10:- ACS-Enable Unit design(RTL)

Fig 15:- multiplexer units 4x1)

IJISRT20MAR486 www.ijisrt.com 1211

Table 1:- Power Performance Summary

Table 2:- Summary Performance of Area and Timing

In this paper vertibi decoder is designed using

[1]. D. Chakraborty, P. Raha, A. Bhattacharya, "Speed

IJISRT20MAR486 www.ijisrt.com 1212

IJISRT20MAR486 www.ijisrt.com 1213

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