Volume 6, Issue 3, March – 2021 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Reduction Techniques for Power and Delay on

Full Adder by XOR Gate Logics Using
Microwind EDA Tool
S.I. Padma, ME,[1] , S. Archana Devi[2] , R.Jenifer[3] , V. Pramma Sathya [4],
[1]
Assistant professor , ECE Department ,PET ENGINEERING COLLEGE , Vallioor.
[2][3][4]
Final year UG students, ECE Department, PET ENGINEERING COLLEGE , Vallioor.

Abstract:- Full adder circuit is central to most digital  XOR gate

circuits that slaves a significant port in the design of XOR represents the inequality function. It is a special
particular integrated circuits. Power dissipation and type of logic the output true if the inputs are different. The
delay are the momentous parameter of the circuits. inputs are same the output is false.XOR gate is made by the
Therefore reducing power consumption and delay in combination of three basic gates (AND gate , OR gate,
full adder and XOR gate using various logics like, NOT gate)
Transmission gate logic(TGL),Pass Transistor
logic(PTL) and static complementary metal oxide The power consumption will be decreased in full adder
semiconductor (CMOS)logic, Dual rail Domino Logic by designing the XOR gate in properways. XOR implements
and Domino Logic , Double Pass Transistor (DPL).The the application oriented digital circuits design.
circuits are designed and implemented, simulated using
Microwind EDA tool. Using the comparative power and
delay analysis, the designer requiredan sufficient adder
design can be select based on the parametercriteria.

Keywords :- Transmission gate logic, Pass, Transistor

Logic , Double Pass Transistor Logic DPL, Domino Logic,
Dual rail domino logic , Microwind EDA.

I. INTRODUCTION

Addition is the term used to describe adding two or

more numbers together. Adder is basic building block of Fig 2 : XOR Gate
most digital system. All field of engineering have role of
adder to produce arithmetic operation. C. Power dissipation
The power dissipation play a major role to design any
A. Adder : circuit.
An adder is acircuit that performs addition of numbers
. Its process is to calculate address , table indices and similar With respect to power there are two major
operation. categories . They are,
1. Static Power Dissipation
B. Full adder :
2. Dynamic Power Dissipation
Full adder is an arithmetic circuit that is used in many
3. Short circuit power dissipation
IC design. The block diagram of full adder is shown above.
It has 3 input and 2 out put.
D. Static Power Dissipation
Static power is the power it can be seen that one of the
Fig 1 : Full adder circuit
transistor is always off when the gate is in either of logic
states. and is generally determined by the formula.
Pstatic=Istatic.Vdd

E. Dynamic power dissipation

Dynamic power dissipation is the modeled by
assuming that the rise and fall time of the step input is much
more then the repetition period. Pdynamic=Pcap+Ptransient
=(CL+C)(Vdd)^2fN^3

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Volume 6, Issue 3, March – 2021 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
F. short circuit power dissipation A Transmission gate is similar to a relay that can
It depends upon charge of capacitor. As the load conduct in both directions or block by a control signal with
capacitance is increased the significance of the power almost any voltage potential. The Transmission Gate Logic
reducedby the capacitive dissipation Pd full adder is called as Zhuang full adder. transmission gate is
Pshort=Ishort.Vdd the CMOS based switch in which PMOS passes a strong 1
but poor 0 and NMOS passes strong 0 but poor 1.When the
G. Delay control voltage is high ,the gate is turned on with both
The delay is defined as the average of the low to High transistors able to conduct. TGL providing a most voltage
time and high to low time and is generally determined by level at the output. because it consumes nearly half the
Tp=t(PLH)+t(PHL) / 2 ability consumed by a standard full adder.

II. PROPOSED METHOD 3. Pass Transistor logic (PTL)

Pass electronic transistor logic (PTL) describes many
In this project ,we are going to design low power logic families employed in the look of integrated circuits. It
full adder by using XOR gate with various techniques. reduces the count of transistors used to make a completely
The six power and delay reduction techniques are, different logic gates, by eliminating not use transistors.
1. Complementary metal oxide semiconductor (CMOS)
logic Transistors are used as switches to pass logic levels
2. Transmission gate logic (TGL) between nodes of a circuit, rather than as switches
3. Pass Transistor Logic (PTL) connected on to offer voltages. This reduces the quantity of
4. Domino Logic active devices
5. Dual Rail Domino Logic
6. Double Pass Transistor Logic (DPL)

1. CMOS Logic
CMOS can be obtained by integrating the NMOS and
PMOS device on the same substrate. It is immune toward
noise occurring condition. It is also used in designing
integrated circuits, microprocessor and microcontroller. The
CMOS provide robustness against voltage scaling. It
operatedhigh reliability and provide required power with
minimum number of transistors.

Fig 5: PTL Full adder

4. Domino logic
Domino logic could be a CMOS-based evolution of
the dynamic logic technique.It purely depends on clock
signal.The clock signal only decide a transistor as a
precharged and evaluation switch. It had been developed to
hurry up circuits, finding the premature cascade downside,
generally by inserting tiny and quick pFETs between
Fig 3 : CMOS Full adder domino stages to constrain the interstage cascade rate to a
curtailed a not require clock interlocks.
2. Transmission gate logic (TGL)

Fig 4:TGL Full adder Fig 6: Domino Logic Full adder

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Volume 6, Issue 3, March – 2021 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
5. Dual rail domino logic III. RESULTS AND DISCUSSION
Dual rail domino provides both inverting and non
inverting functions, added tothat is the clocking power. The circuit of the six different power and delay
Firstly, if the clock for stage i+1 arrives earlier than the reduction techniques of full adder with XOR gate designed
clock for stage I , stage i+1 is in evaluation where as by using MICROWIND tool and its layout be generated
stage I is still in pre-charge. The “precharged” output of with the help Microwind EDA editor and its functionalities
stage I when fed to the gate terminal of the NMOS are verified in each style.
transistors used in stage i+1 turns the aforementioned
NMOS transistors ON and thus the output of the NMOS
Block discharges and remains permanently at logic low,
thus preventing the NMOS block from simulating the
required functionality.

Fig 9:CMOS full adder circuit

Fig 7 : DRDL Full adder

6. Double Pass Transistor logic

DPL represents a PTL family alternative to CPL.This
eliminates problem of the threshold drop and use of
inverting after each block. DPL is shown to boost circuit
performance at reduced offer voltage. Its symmetrical
arrangement and double transmission characteristics
improve the gate speed while not increasing the input
capacitance .we propose a differential logic unit enforced in
CMOS double pass junction transistor logic. The planned
logic unit (LU) is low power and tiny variety of transistors
style. It performs eight logic functions with solely sixteen Fig 10 :power dissipation of CMOS
transistor.

Fig 8 : DPL Full adder Fig 11 : Delay of CMOS full adder

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Volume 6, Issue 3, March – 2021 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig 16: power of PTL full adder

Fig12:TGL Full adder Circuit.

Fig 13 : power of TGL Full adder. Fig 17: delay of PTL full adder

Fig14:Powerof TGL full adder circuit Fig 18: Domino Logic full adder

Fig 15 : delay of TGL output Fig 19: Domino Logic power

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Volume 6, Issue 3, March – 2021 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
IV. CONCLUSION

The project makes a very significant points that are

used while selecting a suitable power and delay reduction
techniques. MICROWIND tool is used to design and
stimulate the circuits at layout level for different
technologies like , Complementary metal oxide
semiconductor (CMOS) , Transmission Gate logic (TGL)
,Pass Transistor logic (PTL) , Domino Logic , Dual Rail
Domino Logic (DRDL) , Double Pass Transistor logic
(DPL) techniques .

Double Pass Transistor logic use only 16 Transistors

which is controlled by the output of circuit itself. It
Fig 20 : Domino Logic delay achieves the reduction in power and delay compared to
other reduction techniques and along with the advantage
of not affecting the dynamic power and use of limited area
requirements since this technique does not require any
additional and monitor circuitry.

REFERENCES

[1]. M Alioto, G Palumbo, “Analysis and comparison of

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[2]. Amol Kashinath Boke,Priyanka
Dabhade,“Analyse low power Wallace multiplier
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Fig21 : DRDL Full adder Circuit
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[3]. Arkadiy Morgenshtein, A Fish, Israel A Wagner, Gate-
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Volume 6, Issue 3, March – 2021 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
[10]. Nabihah Ahmad , Rezaul Hasan, “Lowest power
dissipation in low supply Voltage ” International
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