Its summer break in most universities. I have noticed a clear difference between those who have done hands-on internships over the ones who don't. In semester projects, often the project runs first time in the last night, but in a professional setting one's work is tested more, scrutinized more. The debugging skills, and better ways to approach a problem and write code not only help in final term projects but throughout careers. Moreover working for typical 40hrs per week on same problem not only shows how big a difference concentrated effort can bring in terms of work done, but also helps getting used to the expected work life later.
Quite a few people requested for internships but we ran out of space this year. In the post-covid world, if one couldn't secure internship he can still go through similar experience. Here is a typical flow that I ask internees in the HW design domain to go through:
1- Go through review of logic design course ( https://lnkd.in/eXM3hXW ). If some topic is covered too fast fall back on detailed lecture of that specific topic in course playlist (2016: https://lnkd.in/eVm65q9S and 2020 (covers verilog onwards only): https://lnkd.in/d7BBwcRB )
2- Write verilog codes and test benches of all the examples covered (counters, Fifo, Clock, Simple processor) and simulate to verify it. If an FPGA board can be issued from university lab, test it on FPGA board (otherwise simulation is ok)
From here on we typically decide whether one takes Zynq based training path (which is useful for implementation of DSP based systems. Points 3,4) or processor design path (more useful towards ASIC, Points 5,6,7)
3- For Zynq training, having a Zynq based board with you is essential (There are 100-200$ boards available on Digilent's site). I generally give internees a board ask them to go through first 14 lectures of this playlist ( https://lnkd.in/fyCxqgb )
I typically ask them to understand everything and try it in parallel. And then do the same from their own memory (fall back to lectures only if they forget something) to gain confidence in doing things on their own.
4- Then we decide on some interesting tasks e.g. writing accelerators or up/down converters, using FIR and FFT cores etc. etc.
5- For processor design path, I normally ask them to go through first ~7.5 hrs (before VLIW) of this video ( https://lnkd.in/duiueei4 )
6- After initial 2 hrs of last video, one can start working on writing verilog code of a single cycle RISCV bare minimum core. Run RISCV compiled code on the processor on an FPGA.
7- Next step is pipelining the processor incorporating stalls or bypassing without breaking it.
Typically internship is over before final step, but covering 70% of the path is generally good enough. Feel free to share
50K+ | Software Engineer at Samsung R&D Institute India | TIET'23
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